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FEATURES Excellent Video Specifications (RL = 150 , G = +2) Gain Flatness 0.1 dB to 60 MHz 0.01% Differential Gain Error 0.02 Differential Phase Error Low Power 5.5 mA/Amp Max Power Supply Current (55 mW) High Speed and Fast Settling 600 MHz, -3 dB Bandwidth (G = +1) 500 MHz, -3 dB Bandwidth (G = +2) 1200 V/ s Slew Rate 16 ns Settling Time to 0.1% Low Distortion -65 dBc THD, f C = 5 MHz 33 dBm Third Order Intercept, F1 = 10 MHz -66 dB SFDR, f = 5 MHz -60 dB Crosstalk, f = 5 MHz High Output Drive Over 70 mA Output Current Drives Up to Eight Back-Terminated 75 Loads (Four Loads/Side) While Maintaining Good Differential Gain/Phase Performance (0.01%/0.17 ) Available in 8-Lead Plastic DIP, SOIC and SOIC Packages APPLICATIONS A-to-D Driver Video Line Driver Differential Line Driver Professional Cameras Video Switchers Special Effects RF Receivers PRODUCT DESCRIPTION
Dual 600 MHz, 50 mW Current Feedback Amplifier AD8002
FUNCTIONAL BLOCK DIAGRAM 8-Lead Plastic DIP, SOIC, and SOIC
OUT1 1 -IN1 2 +IN1 3 V- 4 8 V+ 7 OUT2 6 -IN2 5 +IN2
AD8002
The outstanding bandwidth of 600 MHz along with 1200 V/s of slew rate make the AD8002 useful in many general purpose high speed applications where dual power supplies of up to 6 V and single supplies from 6 V to 12 V are needed. The AD8002 is available in the industrial temperature range of -40C to +85C.
1 SIDE 1 0 -1 -2 -3 SIDE 1 -4 -5 SIDE 2 -0.2 -0.3 -0.4 -0.5 1M -6 -7 -8 -9 1G
NORMALIZED FLATNESS - dB
G = +2 RL = 100 VIN = 50mV 0.1 0 -0.1
SIDE 2
10M 100M FREQUENCY - Hz
The AD8002 is a dual, low-power, high-speed amplifier designed to operate on 5 V supplies. The AD8002 features unique transimpedance linearization circuitry. This allows it to drive video loads with excellent differential gain and phase performance on only 50 mW of power per amplifier. The AD8002 is a current feedback amplifier and features gain flatness of 0.1 dB to 60 MHz while offering differential gain and phase error of 0.01% and 0.02. This makes the AD8002 ideal for professional video electronics such as cameras and video switchers. Additionally, the AD8002's low distortion and fast settling make it ideal for buffer high-speed A-to-D converters. The AD8002 offers low power of 5.5 mA/amplifier max (VS = 5 V) and can run on a single 12 V power supply, while capable of delivering over 70 mA of load current. It is offered in an 8-lead plastic DIP, SOIC, and SOIC package. These features make this amplifier ideal for portable and battery-powered applications where size and power are critical. REV. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Figure 1. Frequency Response and Flatness, G = +2
SIDE 1
G = +2 1V STEP
SIDE 2 200mV 5ns
Figure 2. 1 V Step Response, G = +1
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2001
NORMALIZED FREQUENCY RESPONSE - dB
AD8002-SPECIFICATIONS (@ T = 25 C, V =
A S
5 V, RL = 100
, RC1 = 75
Min
, unless otherwise noted.)
AD8002A Typ Max
500 600 500 600 500 600 60 90 60 700 1200 16 2.4 -65 -60 2.0 2.0 18 0.01 0.02 33 14 -66 2.0 2.0 10 5.0 3.0 6 9 25 35 6.0 10
Model Conditions
DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth, N Package R Package RM Package Bandwidth for 0.1 dB Flatness N Package R Package RM Package Slew Rate Settling Time to 0.1% Rise and Fall Time NOISE/HARMONIC PERFORMANCE Total Harmonic Distortion Crosstalk, Output to Output Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error Third Order Intercept 1 dB Gain Compression SFDR DC PERFORMANCE Input Offset Voltage TMIN -TMAX Offset Drift -Input Bias Current TMIN -TMAX +Input Bias Current Open Loop Transresistance INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio Offset Voltage -Input Current +Input Current OUTPUT CHARACTERISTICS Output Voltage Swing Output Current2 Short Circuit Current2 POWER SUPPLY Operating Range Quiescent Current/Both Amplifiers Power Supply Rejection Ratio -Input Current +Input Current TMIN -TMAX VO = 2.5 V TMIN -TMAX +Input -Input +Input VCM = 2.5 V VCM = 2.5 V, TMIN -TMAX VCM = 2.5 V, TMIN -TMAX R L = 150 250 175 G = +2, R F = 750 G = +2, R F = 681 G = +2, R F = 681 G = +2, VO = 2 V Step G = -1, VO = 2 V Step G = +2, VO = 2 V Step G = +2, VO = 2 V Step, RF = 750 fC = 5 MHz, VO = 2 V p-p G = +2, RL = 100 f = 5 MHz, G = +2 f = 10 kHz, RC = 0 f = 10 kHz, +In -In NTSC, G = +2, R L = 150 NTSC, G = +2, R L = 150 f = 10 MHz f = 10 MHz f = 5 MHz G = +2, RF = 750 G = +1, RF = 1.21 k G = +2, RF = 681 G = +1, RF = 953 G = +2, RF = 681 G = +1, RF = 1 k
Unit
MHz MHz MHz MHz MHz MHz MHz MHz MHz V/s V/s ns ns dBc dB nV/Hz pA/Hz pA/Hz % Degree dBm dBm dB mV mV V/C A A A A k k M pF V
900
10 50 1.5 3.2 49 54 0.3 0.2 3.1 70 110 6.0 11.5
1.0 0.9
dB A/V A/V V mA mA V mA dB dB A/V A/V
2.7 85 3.0
TMIN -TMAX +VS = +4 V to +6 V, -VS = -5 V -VS = - 4 V to - 6 V, +VS = +5 V TMIN -TMAX TMIN -TMAX
60 49
10.0 75 56 0.5 0.1
2.5 0.5
NOTES 1 RC is recommended to reduce peaking and minimize input reflections at frequencies above 300 MHz. However, R C is not required. 2 Output current is limited by the maximum power dissipation in the package. See the power derating curves. Specifications subject to change without notice.
-2-
REV. D
AD8002
ABSOLUTE MAXIMUM RATINGS 1 MAXIMUM POWER DISSIPATION
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2 V Internal Power Dissipation2 Plastic DIP Package (N) . . . . . . . . . . . . . . . . . . . . . . . 1.3 W Small Outline Package (R) . . . . . . . . . . . . . . . . . . . . . . 0.9 W SOIC Package (RM) . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 W Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . VS Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . 1.2 V Output Short Circuit Duration . . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves Storage Temperature Range N, R, RM . . . . . -65C to +125C Operating Temperature Range (A Grade) . . . - 40C to +85C Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for device in free air: 8-Lead Plastic DIP Package: JA = 90C/W 8-Lead SOIC Package: JA = 155C/W 8-Lead SOIC Package: JA = 200C/W
The maximum power that can be safely dissipated by the AD8002 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150C. Exceeding this limit temporarily may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 175C for an extended period can result in device failure. While the AD8002 is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (150C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves.
2.0 8-LEAD PLASTIC-DIP PACKAGE
MAXIMUM POWER DISSIPATION - W
8-LEAD SOIC PACKAGE 1.5 TJ = 150 C
1.0
0.5
8-LEAD SOIC PACKAGE
0 -50 -40 -30 -20 -10
0
10
20
30 40
50
60
70
80 90
AMBIENT TEMPERATURE - C
Figure 3. Plot of Maximum Power Dissipation vs. Temperature
ORDERING GUIDE
Model AD8002AN AD8002AR AD8002AR-REEL AD8002AR-REEL7 AD8002ARM AD8002ARM-REEL AD8002ARM-REEL7
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 8-Lead PDIP 8-Lead SOIC 8-Lead SOIC 13" REEL 8-Lead SOIC 7" REEL 8-Lead SOIC 8-Lead SOIC 13" REEL 8-Lead SOIC 7" REEL
Package Option N-8 SO-8 SO-8 SO-8 RM-8 RM-8 RM-8
Brand Code Standard Standard Standard Standard HFA HFA HFA
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8002 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. D
-3-
AD8002-Typical Performance Characteristics
953 +5V 10 F 0.1 F 750 +5V 750 10 F 0.1 F
AD8002
75 VIN PULSE GENERATOR TR/TF = 250ps 50 0.1 F 10 F -5V RL = 100 VIN PULSE GENERATOR TR/TF = 250ps
AD8002
75 50 0.1 F 10 F -5V RL = 100
TPC 1. Test Circuit , Gain = +1
TPC 4. Test Circuit, Gain = +2
SIDE 1
SIDE 1 G = +1 100mV STEP G = +2 100mV STEP
SIDE 2
SIDE 2 20mV 5ns 20mV 5ns
TPC 2. 100 mV Step Response, G = +1
TPC 5. 100 mV Step Response, G = +2
SIDE 1
G = +1 1V STEP
SIDE 1
G = +2 1V STEP
SIDE 2
SIDE 2 200mV 5ns 20mV 5ns
TPC 3. 1 V Step Response, G = +1
TPC 6. 1 V Step Response, G = +2
-4-
REV. D
AD8002
1 NORMALIZED FREQUENCY RESPONSE - dB SIDE 1 NORMALIZED FLATNESS - dB G = +2 RL = 100 VIN = 50mV 0.1 0 -0.1 -0.2 -0.3
681 75 50 50
-20 -30 -40 -50
0 -1 -2 -3
SIDE 2
VIN = -4dBV RL = 100 VS = 5.0V G = +2 RF = 750
OUTPUT SIDE 1
CROSSTALK - dB
-60 -70 -80 -90 -100 -110 -120 100k
OUTPUT SIDE 2
SIDE 1
-4 -5
SIDE 2
-6 -7
-0.4 -0.5 1M
RF 681
-8 -9 1G
10M 100M FREQUENCY - Hz
1M
10M FREQUENCY - Hz
100M
TPC 7. Frequency Response and Flatness, G = +2
TPC 10. Crosstalk (Output-to-Output) vs. Frequency
-50 G = +2 RL = 100 -60
SIDE 1
G=+2 RF = 750 RC = 75 RL = 100
DISTORTION - dBc
-70 2ND HARMONIC -80 3RD HARMONIC -90
SIDE 2
-100
5ns
-110 10k 100k 1M FREQUENCY - Hz 10M 100M
NOTES: SIDE 1: VIN = 0V; 8mV/div RTO SIDE 2: 1V STEP RTO; 400mV/div
TPC 8. Distortion vs. Frequency, G = +2, RL = 100
-60
TPC 11. Pulse Crosstalk, Worst Case, 1 V Step
0.02
DIFF GAIN - %
-70
G = +2 RL = 1k VOUT = 2V p-p
0.01 0.00 -0.01 -0.02 G = +2 RF = 750 NTSC
2 BACK-TERMINATED LOADS (75 )
DISTORTION - dBc
-80 2ND HARMONIC -90
1 BACK-TERMINATED LOAD (150 ) 2 BACK-TERMINATED LOADS (75 )
DIFF PHASE - Degrees
3RD HARMONIC
0.08 0.06 0.04 0.02 0.00 1 2 3 4 5 6 IRE 7 8 9 10 11 1 BACK-TERMINATED LOAD (150 )
-100
-110
-120 10k
100k
1M FREQUENCY - Hz
10M
100M
TPC 9. Distortion vs. Frequency, G = +2, RL = 1 k
TPC 12. Differential Gain and Differential Phase (per Amplifier)
REV. D
-5-
AD8002
2 1 0 VIN = 50mV G = +1 RF = 953 RL = 100 SIDE 1 0 -3 -6 6 3 0 -3 -6 -9 G = +2 RF = 681 VS = 5V RL = 100 -12 -15 -18 -21 500M
INPUT LEVEL - dBV
SIDE 2
GAIN - dB
-1 -2 -3 -4 -5 -6 1M
953 75 50 50
-9 -12 -15 -18 -21 -24 -27 1M
10M
100M FREQUENCY - Hz
1G
10M 100M FREQUENCY - Hz
TPC 13. Frequency Response, G = +1
TPC 16. Large Signal Frequency Response, G = +2
-40 G = +1 RL = 100 VOUT = 2V p-p
9 6
INPUT/OUTPUT LEVEL - dBV
-50
3 0 -3 -6
75
RL = 100 G = +1 RF = 1.21k
DISTORTION - dBc
-60
-70 2ND HARMONIC -80 3RD HARMONIC -90
-9
50
50
-12 -15 -18
1.21k
-100 10k
100k
1M FREQUENCY - Hz
10M
100M
-27 1M
10M 100M FREQUENCY - Hz
500M
TPC 14. Distortion vs. Frequency, G = +1, RL = 100
TPC 17. Large Signal Frequency Response, G = +1
-40 G = +1 RL = 1k
45 40 35 VS = 5V RL = 100
-50 -60
DISTORTION - dBc
30
-70 2ND HARMONIC -80 -90 3RD HARMONIC
GAIN - dB
25 20 15 10 5
G = +100 RF = 1000
G = +10 RF = 499
-100
0 -5 1M
-110 10k
100k
1M FREQUENCY - Hz
10M
100M
10M 100M FREQUENCY - Hz
1G
TPC 15. Distortion vs. Frequency, G = +1, RL = 1 k
TPC 18. Frequency Response, G = +10, G = +100
-6-
REV. D
OUTPUT LEVEL - dBV
AD8002
OUTPUT G = +2 2V STEP RF = 750 RC = 75 G = +2 2V STEP RF = 750 RC = 75 RL = 100 ERROR, (0.05%/DIV)
ERROR, (0.05%/DIV)
OUTPUT
INPUT 400mV 10ns
INPUT 400mV
TPC 19. Short-Term Settling Time
TPC 22. Long-Term Settling Time
3.4 3.3 3.2
4 DEVICE #1
RL = 150 VS = +VOUT |-VOUT| 5V
3 INPUT OFFSET VOLTAGE - mV
OUTPUT SWING - Volts
2 1 DEVICE #2 0 -1 DEVICE #3
3.1 3.0 2.9 2.8 2.7 2.6 2.5 -55
RL = 50 VS = +VOUT |-VOUT| 5V
-2 -3 -55
-35
-15
5
25
45
65
85
105
125
-35
-15
5
25
45
65
85
105
125
JUNCTION TEMPERATURE - C
JUNCTION TEMPERATURE - C
TPC 20. Output Swing vs. Temperature
TPC 23. Input Offset Voltage vs. Temperature
5 4 3 2 1 0 -1 -2 -3 -55 +IN
TOTAL SUPPLY CURRENT - mA
11.5
-IN
INPUT BIAS CURRENT - A
11.0
10.5 VS = 10.0 5V
9.5
-35
-15
5
25
45
65
85
105
125
9.0 -55
-35
-15
5
25
45
65
85
105
125
JUNCTION TEMPERATURE - C
JUNCTION TEMPERATURE - C
TPC 21. Input Bias Current vs. Temperature
TPC 24. Total Supply Current vs. Temperature
REV. D
-7-
AD8002
120 115
SHORT CIRCUIT CURRENT - mA
100 RF = 750 RC = 75 VS = 5.0V POWER = 0dBm (223.6mVrms) G = +2 RbT = 0 RbT = 50
110 105 100 95 90 85 80 75 70 -55
0.01 10
|SINK ISC|
SOURCE ISC
RESISTANCE -
1
0.1
-35
-15
5
25
45
65
85
105
125
10k
100k
JUNCTION TEMPERATURE - C
1M 10M FREQUENCY - Hz
100M
1G
TPC 25. Short Circuit Current vs. Temperature
TPC 28. Output Resistance vs. Frequency
100
100
-3dB BANDWIDTH SIDE 1 0.2 SIDE 2
1 0 -1 -2 0.1dB FLATNESS 0 -0.1 -0.2 -0.3 VS = 5V VIN = 50mV G = -1 RL = 100 RF = 549 SIDE 2 SIDE 1 -3 -4 -5 -6 -7 -8
OUTPUT VOLTAGE - dB
NOISE CURRENT - pA/ Hz
NOISE VOLTAGE - nV/ Hz
INVERTING CURRENT VS =
5V
0.1
10 NONINVERTING CURRENT VS = 5V
10
VOLTAGE NOISE VS =
5V
1 10 100 1k FREQUENCY - Hz 10k
1 100k
1M
10M 100M FREQUENCY - Hz
-9 1G
TPC 26. Noise vs. Frequency
TPC 29. -3 dB Bandwidth vs. Frequency, G = -1
-48 -49 -50 -CMRR
-50.0 -52.5 -PSRR -55.0 -57.5
CMRR - dB
PSRR - dB
-51 -52 -53 -54 +CMRR
-60.0 -62.5 -65.0 -67.5 -70.0
2V SPAN CURVES ARE FOR WORSTCASE CONDITION WHERE ONE SUPPLY IS VARIED WHILE THE OTHER IS HELD CONSTANT.
-55 -56 -55
+PSRR -72.5 -75.0 -55
-35
-15 5 25 45 65 85 JUNCTION TEMPERATURE - C
105
125
-35
-15
5
25
45
65
85
105
125
JUNCTION TEMPERATURE - C
TPC 27. CMRR vs. Temperature
TPC 30. PSRR vs. Temperature
-8-
REV. D
AD8002
0
VIN
0 -10
50
-10
604
604
VIN = 200mV G = +2
-20 -30
-20
CMRR - dB
0.1 F -5V
PSRR - dB
57.6
154 154
-40 -50 -60
-PSRR
-30
-40
SIDE 1 SIDE 2 VS = 5.0V RL = 100 VIN = 200mV
+PSRR
-70 -80 -90 30k 100k
-50
-60 1M 10M 100M FREQUENCY - Hz 1G
1M
10M FREQUENCY - Hz
100M
500M
TPC 31. CMRR vs. Frequency
TPC 34. PSRR vs. Frequency
SIDE 1
G = -1 RF = 576 RG = 576 RC = 50
SIDE 1
G = -2 2V STEP RF = 549
SIDE 2
SIDE 2
400mV
5ns
400mV
5ns
TPC 32. 2 V Step Response, G = -1
TPC 35. 2 V Step Response, G = -2
576 576 50 54.9 50
61.9 50 274
549
50
SIDE 1
SIDE 1
G = -1 100mV STEP RF = 549
SIDE 2 G = -1 RF = 576 RG = 576 RC = 50 RL = 100
SIDE 2
20mV
5ns
20mV
5ns
TPC 33. 100 mV Step Response, G = -1
TPC 36. 100 mV Step Response, G = -2
REV. D
-9-
AD8002
THEORY OF OPERATION Printed Circuit Board Layout Considerations
A very simple analysis can put the operation of the AD8002, a current feedback amplifier, in familiar terms. Being a current feedback amplifier, the AD8002's open-loop behavior is expressed as transimpedance, VO/I-IN, or TZ. The open-loop transimpedance behaves just as the open-loop voltage gain of a voltage feedback amplifier, that is, it has a large dc value and decreases at roughly 6 dB/octave in frequency. Since the RIN is proportional to 1/gm, the equivalent voltage gain is just TZ x gm, where the gm in question is the transconductance of the input stage. This results in a low open-loop input impedance at the inverting input, a now familiar result. Using this amplifier as a follower with gain, Figure 4, basic analysis yields the following result.
As expected for a wideband amplifier, PC board parasitics can affect the overall closed-loop performance. Of concern are stray capacitances at the output and the inverting input nodes. If a ground plane is to be used on the same side of the board as the signal traces, a space (5 mm min) should be left around the signal lines to minimize coupling. Additionally, signal lines connecting the feedback and gain resistors should be short enough so that their associated inductance does not cause high frequency gain errors. Line lengths on the order of less than 5 mm are recommended. If long runs of coaxial cable are being driven, dispersion and loss must be considered.
Power Supply Bypassing
TZ (S ) VO =Gx VIN TZ (S ) + G x RIN + R1 G = 1+ R1 RIN = 1 / g m 50 R2
R1
Adequate power supply bypassing can be critical when optimizing the performance of a high-frequency circuit. Inductance in the power supply leads can form resonant circuits that produce peaking in the amplifier's response. In addition, if large current transients must be delivered to the load, bypass capacitors (typically greater than 1 F) will be required to provide the best settling time and lowest distortion. A parallel combination of 4.7 F and 0.1 F is recommended. Some brands of electrolytic capacitors will require a small series damping resistor 4.7 for optimum results.
DC Errors and Noise
R2 RIN VOUT
VIN
Figure 4.
Recognizing that G x RIN << R1 for low gains, it can be seen to the first order that bandwidth for this amplifier is independent of gain (G). Considering that additional poles contribute excess phase at high frequencies, there is a minimum feedback resistance below which peaking or oscillation may result. This fact is used to determine the optimum feedback resistance, R F. In practice parasitic capacitance at the inverting input terminal will also add phase in the feedback loop, so picking an optimum value for R F can be difficult. Achieving and maintaining gain flatness of better than 0.1 dB at frequencies above 10 MHz requires careful consideration of several issues.
Choice of Feedback and Gain Resistors
There are three major noise and offset terms to consider in a current feedback amplifier. For offset errors, refer to the equation below. For noise error, the terms are root-sum-squared to give a net output error. In the circuit shown in Figure 5 they are input offset (VIO), which appears at the output multiplied by the noise gain of the circuit (1 + R F/R I), noninverting input current (IBN x RN), also multiplied by the noise gain, and the inverting input current, which, when divided between RF and RI and subsequently multiplied by the noise gain, always appears at the output as IBN x RF. The input voltage noise of the AD8002 is a low 2 nV/Hz. At low gains, though, the inverting input current noise times RF is the dominant noise source. Careful layout and device matching contribute to better offset and drift specifications for the AD8002 compared to many other current feedback amplifiers. The typical performance curves in conjunction with the equations below can be used to predict the performance of the AD8002 in any application.
R R VOUT = VIO x 1 + F I BN x RN x 1 + F I BI x RF RI RI
RF IBI
The fine scale gain flatness will, to some extent, vary with feedback resistance. It, therefore, is recommended that once optimum resistor values have been determined, 1% tolerance values should be used if it is desired to maintain flatness over a wide range of production lots. In addition, resistors of different construction have different associated parasitic capacitance and inductance. Surface mount resistors were used for the bulk of the characterization for this data sheet. It is not recommended that leaded components be used with the AD8002.
RI
RN
IBN
VOUT
Figure 5. Output Offset Voltage
-10-
REV. D
AD8002
Driving Capacitive Loads
-45 -50 G = +2 F1 = 10MHz F2 = 12MHz 2F2 - F1 -60 2F1 - F2 -65 -70 -75 -80 -8 -7 -6 -5 -4
THIRD ORDER IMD - dBc
The AD8002 was designed primarily to drive nonreactive loads. If driving loads with a capacitive component is desired, best frequency response is obtained by the addition of a small series resistance as shown in Figure 6.
909
-55
RSERIES IN RL 500 CL
Figure 6. Driving Capacitive Loads
-3 -2 -1 0 1 INPUT POWER - dBm
2
3
4
5
6
Figure 7 shows the optimum value for RSERIES versus capacitive load. It is worth noting that the frequency response of the circuit when driving large capacitive loads will be dominated by the passive roll-off of RSERIES and CL.
40
Figure 8. Third Order IMD; F1 = 10 MHz, F2 = 12 MHz
Operation as a Video Line Driver
30
RSERIES - V
20
The AD8002 has been designed to offer outstanding performance as a video line driver. The important specifications of differential gain (0.01%) and differential phase (0.02) meet the most exacting HDTV demands for driving one video load with each amplifier. The AD8002 also drives four back-terminated loads (two each), as shown in Figure 9, with equally impressive performance (0.01%, 0.07). Another important consideration is isolation between loads in a multiple load application. The AD8002 has more than 40 dB of isolation at 5 MHz when driving two 75 back-terminated loads.
750 750 +VS 4.7 F + 75 75 CABLE VOUT #1 75
10
0 0
0.1 F
5 10 CL - pF 15 20 25
Figure 7. Recommended RSERIES vs. Capacitive Load
Communications
1/2 AD8002
0.1 F 75 CABLE VIN 75 -VS
75
75 CABLE VOUT #2 75
Distortion is a key specification in communications applications. Intermodulation distortion (IMD) is a measure of the ability of an amplifier to pass complex signals without the generation of spurious harmonics. The third order products are usually the most problematic since several of them fall near the fundamentals and do not lend themselves to filtering. Theory predicts that the third order harmonic distortion components increase in power at three times the rate of the fundamental tones. The specification of third order intercept as the virtual point where fundamental and harmonic power are equal is one standard measure of distortion performance. Op amps used in closed-loop applications do not always obey this simple theory. At a gain of two, the AD8002 has performance summarized in Figure 8. Here the worst third order products are plotted versus. input power. The third order intercept of the AD8002 is 33 dBm at 10 MHz.
4.7 F
1/2 AD8002
750 750
75
75 CABLE VOUT #3 75
75
75 CABLE VOUT #4 75
Figure 9. Video Line Driver
REV. D
-11-
AD8002
Driving A-to-D Converters
The AD8002 is well suited for driving high-speed analog-todigital converters such as the AD9058. The AD9058 is a dual 8-bit 50 MSPS ADC. In Figure 10, the AD8002 is shown driving the inputs of the AD9058 which are configured for 0 V to 2 V ranges. Bipolar input signals are buffered, amplified (-2x), and offset (by 1.0 V) into the proper input range of the ADC. Using
the AD9058's internal 2 V reference connected to both ADCs as shown in Figure 10 reduces the number of external components required to create a complete data acquisition system. The 20 resistors in series with ADC inputs are used to help the AD8002s drive the 10 pF ADC input capacitance. The AD8002 adds only 100 mW to the power consumption, while not limiting the performance of the circuit.
ENCODE 10 ENCODE A 549 ANALOG IN A 0.5V 274 8 38 -VREF A -VREF B AIN A 36 ENCODE B +VS 50
74ACT04
1k 10pF
5, 9, 22, 24, 37, 41 0.1 F RZ1 18 17 15 14 13 12 11 RZ2 28 29 31 32 33 34 30 16
+5V
1.1k -2V
50
1/2 AD8002
20
6
D0A (LSB)
2
AD707
0.1 F 20k 1.1k 549 ANALOG IN B 0.5V 274
+VINT +VREF A +VREF B D7A (MSB)
74ACT 273 74ACT 273
-5V 1N4001
8
20k 0.1 F
3 43
AD9058
(J-LEAD) D0B (LSB)
50
1/2 AD8002
20
40
AIN B
8
1 COMP 0.1 F D7B (MSB) -VS RZ1, RZ2 = 2,000 SIP (8-PKG) 4,19, 21 25, 27, 42
35 7, 20, 26, 39 0.1 F CLOCK
Figure 10. AD8002 Driving a Dual A-to-D Converter
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REV. D
AD8002
Single-Ended-to-Differential Driver Using an AD8002
The two halves of an AD8002 can be configured to create a single-ended-to-differential high-speed driver with a -3 dB bandwidth in excess of 200 MHz, as shown in Figure 11. Although the individual op amps are each current feedback, the overall architecture yields a circuit with attributes normally associated with voltage feedback amplifiers, while offering the speed advantages inherent in current feedback amplifiers. In addition, the gain of the circuit can be changed by varying a single resistor, RF, which is often not possible in a dual op amp differential driver.
CC 0.5-1.5pF RF 511
With a feedback resistor RF, an input resistor RG, and grounding of the +input of Op Amp #2, a feedback amplifier is formed. This configuration is just like a voltage feedback amplifier in an inverting configuration if only Output #2 is considered. The addition of Output #1 makes the amplifier differential output. The differential gain of this circuit is:
G=
RF R x 1 + A RG RB
RG 511 VIN
OP AMP #1 1/2 AD8002
RA 511 RB 511 RB 511
50 OUTPUT #1
The RF /RG term is the gain of the overall op amp configuration and is the same as for an inverting op amp except for the polarity. If Output #1 is used as the output reference, the gain is positive. The 1 + RA/RB term is the noise gain of each individual op amp in its noninverting configuration. The resulting architecture offers several advantages. First, the gain can be changed by changing a single resistor. Changing either RF or RG will change the gain as in an inverting op amp circuit. For most types of differential circuits, more than one resistor must be changed to change gain and still maintain good CMR.
RA 511
1/2 AD8002 OP AMP #2
50 OUTPUT #2
Figure 11. Differential Line Driver
Reactive elements can be used in the feedback network. This is in contrast to current feedback amplifiers that restrict the use of reactive elements in the feedback. The circuit described requires about 0.9 pF of capacitance in shunt across RF in order to optimize peaking and realize a -3 dB bandwidth of more than 200 MHz. The peaking exhibited by the circuit is very sensitive to the value of this capacitor. Parasitics in the board layout on the order of tenths of picofarads will influence the frequency response and the value required for the feedback capacitor, so a good layout is essential. The shunt capacitor type selection is also critical. A good microwave type chip capacitor with high Q was found to yield best performance. The part selected for this circuit was a muRata Erie part number MA280R9B. The distortion was measured at 20 MHz with a 3 V p-p input and a 100 load on each output. For Output #1 the distortion is -37 dBc and -41 dBc for the second and third harmonics respectively. For Output #2 the second harmonic is -35 dBc and the third harmonic is -43 dBc.
6 CC = 0.9pF 4 2 0
The current feedback nature of the op amps, in addition to enabling the wide bandwidth, provides an output drive of more than 3 V p-p into a 20 load for each output at 20 MHz. On the other hand, the voltage feedback nature provides symmetrical high impedance inputs and allows the use of reactive components in the feedback network. The circuit consists of the two op amps, each configured as a unity gain follower by the 511 RA feedback resistors between each op amp's output and inverting input. The output of each op amp has a 511 RB resistor to the inverting input of the other op amp. Thus, each output drives the other op amp through a unity gain inverter configuration. By connecting the two amplifiers as cross-coupled inverters, their outputs are freed to be equal and opposite, assuring zero-output common-mode voltage. With this circuit configuration, the common-mode signal of the outputs is reduced. If one output moves slightly higher, the negative input to the other op amp drives its output to go slightly lower and thus preserves the symmetry of the complementary outputs, which reduces the common-mode signal. The commonmode output signal was measured to be -50 dB at 1 MHz. Looking at this configuration overall, there are two high impedance inputs (the + inputs of each op amp), two low impedance outputs, and high open-loop gain. If we consider the two noninverting inputs and just the output of Op Amp #2, the structure looks like a voltage feedback op amp having two symmetrical, high-impedance inputs, and one output. The +input to Op Amp #2 is the noninverting input (it has the same polarity as Output #2) and the +input to Amplifier #1 is the inverting input (opposite polarity of Output #2).
OUTPUT - dB
-2 -4 -6 OUT+ -8 -10 OUT- -12 -14 1M
10M 100M FREQUENCY - Hz
1G
Figure 12. Differential Driver Frequency Response
REV. D
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AD8002
Layout Considerations
RF +VS RG IN RT RS -VS RBT OUT
The specified high-speed performance of the AD8002 requires careful attention to board layout and component selection. Proper RF design techniques and low parasitic component selection are mandatory. The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low impedance ground path. The ground plane should be removed from the area near the input pins to reduce stray capacitance. Chip capacitors should be used for supply bypassing (see Figure 13). One end should be connected to the ground plane and the other within 1/8 in. of each power pin. An additional large tantalum electrolytic capacitor (4.7 F-10 F) should be connected in parallel, but not necessarily so close, to supply current for fast, large-signal changes at the output. The feedback resistor should be located close to the inverting input pin in order to keep the stray capacitance at this node to a minimum. Capacitance variations of less than 1 pF at the inverting input will significantly affect high-speed performance. Stripline design techniques should be used for long signal traces (greater than about 1 in.). These should be designed with a characteristic impedance of 50 or 75 and be properly terminated at each end.
Inverting Configuration
+VS C1 0.1 F C2 0.1 F -VS C3 10 F C4 10 F
Supply Bypassing
RF +VS RG RBT IN *RC RT OUT
-VS *SEE TABLE I
Noninverting Configuration
Figure 13. Inverting and Noninverting Configurations
Table I. Recommended Component Values
AD8002AN (DIP) Gain Component RF () RG () RBT (Nominal) () RC ()* RS () RT (Nominal) () Small Signal BW (MHz) 0.1 dB Flatness (MHz) -10 499 49.9 49.9 49.9 - 270 45 -2 549 274 49.9 49.9 61.9 380 80 -1 576 576 49.9 49.9 54.9 410 130 +1 1210 - 49.9 75 49.9 600 35 +2 750 750 49.9 75 49.9 500 60 +10 499 54.9 49.9 0 49.9 170 24 +100 1000 10 49.9 0 49.9 17 3 -10 499 49.9 49.9 49.9 - 250 50 -2 499 249 49.9 49.9 61.9 410 100
AD8002AR (SOIC) Gain -1 549 549 49.9 49.9 54.9 410 100 +1 953 - 49.9 75 49.9 600 35 +2 681 681 49.9 75 49.9 500 90 +10 499 54.9 49.9 0 49.9 170 24 +100 1000 10 49.9 0 49.9 17 3
AD8002ARM ( SOIC) Gain Component RF () RG () RBT (Nominal) () RC ()* RS () RT (Nominal) () Small Signal BW (MHz) 0.1 dB Flatness (MHz) -10 499 49.9 49.9 49.9 - 270 60 -2 499 249 49.9 49.9 61.9 400 100 -1 590 590 49.9 49.9 49.9 410 100 +1 1000 - 49.9 75 49.9 600 35 +2 681 681 49.9 75 49.9 450 70 +10 499 54.9 49.9 0 49.9 170 35 +100 1000 10 49.9 0 49.9 19 3
*RC is recommended to reduce peaking, and minimizes input reflections at frequencies above 300 MHz. However, R C is not required.
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REV. D
AD8002
Figure 14. Board Layout (Silkscreen)
REV. D
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AD8002
Figure 15. Board Layout (Component Layer)
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REV. D
AD8002
Figure 16. Board Layout (Solder Side) (Looking through the Board)
REV. D
-17-
AD8002
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP (N-8)
0.430 (10.92) 0.348 (8.84)
8 5
0.280 (7.11) 0.240 (6.10) 0.325 (8.25) 0.300 (7.62) 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93)
1
4
PIN 1
0.100 (2.54) BSC
0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93)
0.022 (0.558) 0.070 (1.77) SEATING 0.014 (0.356) 0.045 (1.15) PLANE
8-Lead SOIC (SO-8)
0.1968 (5.00) 0.1890 (4.80)
8 5 4
0.1574 (4.00) 0.1497 (3.80) PIN 1
1
0.2440 (6.20) 0.2284 (5.80)
0.0500 (1.27) BSC 0.0098 (0.25) 0.0040 (0.10) SEATING PLANE 0.0688 (1.75) 0.0532 (1.35) 0.0192 (0.49) 0.0138 (0.35) 8 0.0098 (0.25) 0 0.0075 (0.19)
0.0196 (0.50) 0.0099 (0.25)
45
0.0500 (1.27) 0.0160 (0.41)
8-Lead SOIC (RM-8)
0.122 (3.10) 0.114 (2.90)
8
5
0.122 (3.10) 0.114 (2.90)
1 4
0.199 (5.05) 0.187 (4.75)
PIN 1 0.0256 (0.65) BSC 0.120 (3.05) 0.112 (2.84) 0.006 (0.15) 0.002 (0.05) 0.018 (0.46) SEATING 0.008 (0.20) PLANE 0.043 (1.09) 0.037 (0.94) 0.011 (0.28) 0.003 (0.08) 0.120 (3.05) 0.112 (2.84) 33 27
0.028 (0.71) 0.016 (0.41)
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REV. D
Revision History- AD8002
Location Page
Data Sheet changed from REV. C to REV. D. MAX RATINGS changed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
REV. D
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C01044b-0-4/01(D)
PRINTED IN U.S.A.

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